View IP4778CZ38V_4595174.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
Rev. 02 -- 12 February 2009 Product data sheet
1. General description
The IP4778CZ38 is designed for HDMI receiver host interface protection. The IP4778CZ38 includes DDC buffering, slew rate acceleration and decoupling, Hot Plug control, backdrive protection, CEC slew rate control, optional multiplexing of DDC signals, and high-level ESD protection diodes for all HDMI signals. The DDC lines are buffered using a new buffering concept which decouples the internal capacitive load from the external capacitive load. This allows higher PCB design flexibility for the DDC lines with respect to the maximum load of 50 pF specified in the HDMI 1.3 specification. This buffering also boosts the DDC signals, allowing the use of longer HDMI cables having a higher capacitive load than 700 pF. The CEC slew rate limiter prevents ringing on the CEC line and greatly reduces the number of discrete components needed by the CEC application. HDMI receiver and system GPIO applications are simplified by an internal Hot Plug driver module and Hot Plug control. The DDC, Hot Plug and CEC lines are backdrive protected to guarantee HDMI interface signals are not pulled down if the system is powered down or enters Standby mode. All TMDS intra-pairs are protected by a special diode configuration offering a low line capacitance of 0.7 pF only (to ground) and 0.05 pF between the TMDS pairs. These diodes provide protection to components downstream from ESD voltages of up to 8 kV contact in accordance with the IEC 61000-4-2, level 4 standard.
2. Features
I I I I I I I I I I I HDMI 1.3 compliant Pb-free and RoHS compliant Robust ESD protection without degradation after several ESD strikes Low leakage even after several hundred ESD discharges Very high diode switching speed (ns) and low line capacitance of 0.7 pF to ground and 0.05 pF between channels ensures signal integrity DDC capacitive decoupling between system side and HDMI connector side and drive cable buffering with capacitive load (> 700 pF) Hot Plug control for direct connection to system GPIO CEC ringing prevention by slew rate limiter DDC and Hot Plug enable signal for multiplexing and backdrive protection All TMDS lines with integrated rail-to-rail clamping diodes with downstream ESD protection of 8 kV in accordance with IEC 61000-4-2, level 4 Matched 0.5 mm trace spacing
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
I Component count reduction of HDMI receiver application I Highest integration in a small footprint, PCB-level, optimized RF routing, 38-pin TSSOP lead-free package I Choice of system compatible or RF routing optimized pinning variants
3. Applications
I The IP4778CZ38 can be used for a wide range of HDMI sink devices e.g.: N TV N Projectors N PC monitors N HDMI buffer modules (extensions of HDMI cable length) N HDMI picture performance quality enhancer modules
4. Ordering information
Table 1. Ordering information Package Name IP4778CZ38 IP4778CZ38/V TSSOP38 Description plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm Version SOT510-1 Type number
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
2 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
5. Functional diagram
TMDS_D2+ TMDS_D1+ TMDS_BIAS TMDS_D0+ TMDS_CLK+ 5V0
TMDS_D2-
TMDS_D1-
TMDS_GND
TMDS_D0-
TMDS_CLK-
TMDS_BIAS
VCC(5V0)
VCC(3V3)
TMDS_BIAS
VCC(5V0)
SLEW RATE ACCELERATOR HOT_PLUG_DET_OUT
10 A
HOT_PLUG_DET_IN DDC_CLK_OUT
ENABLE DDC_CLK_IN
TMDS_BIAS
VCC(3V3)
TMDS_BIAS
VCC(5V0)
SLEW RATE ACCELERATOR CEC_OUT CEC_IN ENABLE DDC_DAT_OUT SLEW RATE LIMITER DDC_DAT_IN
001aae863
Fig 1.
Functional diagram
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
3 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
6. Pinning information
6.1 Pinning
VCC(5V0) ENABLE GND TMDS_D2+ n.c. TMDS_GND TMDS_D1+ n.c. TMDS_GND
1 2 3 4 5 6 7 8 9
38 TMDS_BIAS 37 VCC(3V3) 36 GND 35 n.c. 34 TMDS_D2- 33 TMDS_GND 32 n.c. 31 TMDS_D1- 30 TMDS_GND
TMDS_D0+ 10 n.c. 11 TMDS_GND 12 TMDS_CLK+ 13 n.c. 14 TMDS_GND 15 CEC_IN 16 DDC_CLK_IN 17 DDC_DAT_IN 18 HOT_PLUG_DET_IN 19
IP4778CZ38
29 n.c. 28 TMDS_D0- 27 TMDS_GND 26 n.c. 25 TMDS_CLK- 24 TMDS_GND 23 CEC_OUT 22 DDC_CLK_OUT 21 DDC_DAT_OUT 20 HOT_PLUG_DET_OUT
001aag032
Fig 2.
Pin configuration of IP4778CZ38
VCC(5V0) ENABLE GND TMDS_D2+ TMDS_GND n.c. TMDS_D1+ TMDS_GND n.c.
1 2 3 4 5 6 7 8 9
38 TMDS_BIAS 37 VCC(3V3) 36 GND 35 n.c. 34 TMDS_GND 33 TMDS_D2- 32 n.c. 31 TMDS_GND 30 TMDS_D1-
TMDS_D0+ 10 TMDS_GND 11 n.c. 12 TMDS_CLK+ 13 TMDS_GND 14 n.c. 15 CEC_IN 16 DDC_CLK_IN 17 DDC_DAT_IN 18 HOT_PLUG_DET_IN 19
IP4778CZ38/V
29 n.c. 28 TMDS_GND 27 TMDS_D0- 26 n.c. 25 TMDS_GND 24 TMDS_CLK- 23 CEC_OUT 22 DDC_CLK_OUT 21 DDC_DAT_OUT 20 HOT_PLUG_DET_OUT
001aag031
Fig 3.
IP4778CZ38_2
Pin configuration of IP4778CZ38/V
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
4 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
6.2 Pin description
Table 2. Symbol VCC(5V0) ENABLE GND TMDS_D2+ TMDS_GND n.c. TMDS_D1+ TMDS_GND n.c. TMDS_D0+ TMDS_GND n.c. TMDS_CLK+ TMDS_GND n.c. CEC_IN DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN HOT_PLUG_DET_OUT DDC_DAT_OUT DDC_CLK_OUT CEC_OUT TMDS_CLK- TMDS_GND n.c. TMDS_D0- TMDS_GND n.c. TMDS_D1- TMDS_GND
IP4778CZ38_2
Pin description Pin IP4778CZ38 1 2 3 4 6 5 7 9 8 10 12 11 13 15 14 16 17 18 19 20 21 22 23 25 24 26 28 27 29 31 30 IP4778CZ38/V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 supply voltage for DDC and Hot Plug circuits enable for DDC and Hot Plug circuits ground for DDC, Hot Plug and CEC circuits[1] ESD protection TMDS channel D2+[2] ground for TMDS channel[1] not connected[2] ESD protection TMDS channel D1+[2] ground for TMDS channel[1] not connected[2] ESD protection TMDS channel D0+[2] ground for TMDS channel[1] not connected[2] ESD protection TMDS channel CLK+[2] ground for TMDS channel[1] not connected[2] CEC signal input to system controller[3] DDC clock input to system controller[3] DDC data input to system controller[3] Hot Plug Detect input from system GPIO[3] Hot Plug Detect output to HDMI connector[4] DDC data output to HDMI connector[4] DDC clock output to HDMI connector[4] CEC signal output to HDMI connector[3] ESD protection TMDS channel CLK-[2] ground for TMDS channel[1] not connected[2] ESD protection TMDS channel D0-[2] ground for TMDS channel[1] not connected[2] ESD protection TMDS channel D1-[2] ground for TMDS channel[1]
(c) NXP B.V. 2009. All rights reserved.
Description
Product data sheet
Rev. 02 -- 12 February 2009
5 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
Pin description ...continued Pin IP4778CZ38 IP4778CZ38/V 32 33 34 35 36 37 38 not connected[2] ESD protection TMDS channel D2-[2] ground for TMDS channel[1] not connected[2] ground for DDC, Hot Plug and CEC circuits[1] supply voltage for CEC circuit bias input for TMDS ESD protection. This pin must be connected to a 0.1 F capacitor. 32 34 33 35 36 37 38 Description
Table 2. Symbol n.c.
TMDS_D2- TMDS_GND n.c. GND VCC(3V3) TMDS_BIAS
[1] [2] [3] [4]
Pins GND and TMDS_GND are internally connected. This pin must always be connected to the IC pin located opposite via a PCB track to guarantee correct functionality; see Figure 15. VCC(3V3) referenced logic level in. VCC(5V0) referenced logic level out.
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI VESD Parameter supply voltage input voltage electrostatic discharge voltage at input pins connector side pins (to ground); IEC 61000-4-2, level 4 contact board side pins; IEC 61000-4-2, level 1 contact Ptot Tstg
[1]
[2] [1]
Conditions
Min GND - 0.5 GND - 0.5
Max 5.5 5.5
Unit V V
-8 -2 -55
+8 +2 8 +125
kV kV mW C
total power dissipation storage temperature
DDC operating at 100 kHz
Connector side pins: TMDS_D2+, TMDS_D2-, TMDS_D1+, TMDS_D1-, TMDS_D0+, TMDS_D0-, TMDS_CLK+, TMDS_CLK-, CEC_OUT, DDC_DAT_OUT and DDC_CLK_OUT, HOT_PLUG_DET_OUT. Board side pins: CEC_IN, DDC_DAT_IN and DDC_CLK_IN, HOT_PLUG_DET_IN, ENABLE.
[2]
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
6 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
8. Static characteristics
Table 4. TMDS protection circuit Tamb = 25 C; unless otherwise specified. Symbol Zener diode VBRzd Rdyn Zener diode breakdown voltage dynamic resistance I = 1 mA I = 1 A; IEC 61000-4-5/9 positive transient negative transient Protection diode Ibck IL(r) VF VCL(ch)trt(pos) back current reverse leakage current forward voltage positive transient channel clamping voltage TMDS channel capacitance TMDS channel capacitance difference VESD = 8 kV per IEC 61000-4-2; voltage 30 ns after trigger VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V
[1]
Parameter
Conditions
Min 6
Typ -
Max 9
Unit V
-
2.4 1.3 0.1 1 0.7 8
5 -
A A V V
from pins TMDS_x to pin TMDS_BIAS; VCC(5V0) = 0 V; VCC(3V3) = 0 V VI = 3.0 V
TMDS channel: pins TMDS_x Cch(TMDS) Cch(TMDS) Cch(mutual)
[2] [2]
-
0.7 0.05 0.07
-
pF pF pF
mutual channel capacitance between signal pin TMDS_x and pin n.c.; VCC(5V0) = 0 V; f = 1 MHz; Vbias = 2.5 V
[2]
[1] [2]
This measurement is performed with a 0.1 F external capacitor on pin TMDS_BIAS. This parameter is guaranteed by design.
Table 5. DDC circuit VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VCC(5V0) VCC(3V3) ICC(5V0) Parameter supply voltage (5.0 V) supply voltage (3.3 V) supply current (5.0 V) VCC(5V0) = 5.5 V; both channels HIGH: DDC_DAT_OUT = VCC(5V0); DDC_CLK_OUT = VCC(5V0) VCC(5V0) = 5.5 V; both channels LOW: DDC_DAT_IN = GND; DDC_CLK_IN = GND; DDC_DAT_OUT = open; DDC_CLK_OUT = open ICC(3V3) supply current (3.3 V) no pull-up resistor connected to VCC(3V3) Conditions Min 4.5 2.7 Typ Max 5.0 3.3 0.5 5.5 5.5 1.0 Unit V V mA Supplies: pins VCC(5V0) and VCC(3V3)
-
0.5
1.0
mA
-
-
0.1
A
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
7 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
Table 5. DDC circuit ...continued VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side: pins DDC_CLK_OUT and DDC_DAT_OUT Used as input VIH VIL IIL VIK ILI Ci HIGH-level input voltage LOW-level input voltage LOW-level input current input clamping voltage input leakage current input capacitance VI = 0.2 V Ii = -18 mA VI = 3.6 V VI = 3 V or 0 V VCC(3V3) = 3.3 V VCC(3V3) = 3.0 V Used as output VOL IOH Co LOW-level output voltage HIGH-level output current output capacitance IOL = 100 A or 6 mA VO = 3.6 V VI = 3 V or 0 V VCC(3V3) = 3.3 V VCC(3V3) = 3.0 V Connector side: pins DDC_CLK_IN and DDC_DAT_IN Used as input VIH VIL IIL VIK ILI Ci HIGH-level input voltage LOW-level input voltage LOW-level input current input clamping voltage input leakage current input capacitance DDC_DAT_OUT, DDC_CLK_OUT, VI = 0.2 V II = -18 mA VI = 3.6 V VI = 3 V or 0 V VCC(3V3) = 3.3 V VCC(3V3) = 3.0 V Used as output VOL IOH Co LOW-level output voltage HIGH-level output current output capacitance IOL = 100 A or 3 mA VO = 3.6 V VI = 3 V or 0 V VCC(3V3) = 3.3 V VCC(3V3) = 3.0 V 8 8 10 10 pF pF 700 1 mV A 7 7 9 9 pF pF 410 400 10 -1.2 1 mV mV A V A 8 8 10 10 pF pF 200 1 mV A 8 8 10 10 pF pF 0.7 x VCC(3V3) -0.5 5.5 0.3 x VCC(3V3) 1 -1.2 1 V V A V A
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
8 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
Table 6. CEC circuit VCC(3V3) = 2.7 V o 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol CI(ch-GND)(levsh) SRr N-FET Von on-state voltage drop N-FET state = on; VCC(3V3) = 2.5 V; VS = GND; IDS = 3 mA
[2]
Parameter level shifting input capacitance from channel to ground rising slew rate
Conditions VCC(3V3) = 0 V; f = 1 MHz; Vbias = 2.5 V VI > 1.8 V
[1]
Min -
Typ 12 10 125
Max 16 140
Unit pF mV/s mV
Board side: input pin CEC_IN
Connector side: output pin CEC_OUT ILI Rdyn input leakage current dynamic resistance I = 1 A; IEC 61000-4-5/9 positive transient negative transient VCL(ch)trt(pos) positive transient channel clamping voltage VESD = 8 kV per IEC 61000-4-2; voltage 30 ns after trigger; Tamb = 25 C
[3]
-1 -
+0.1 2.4 1.3 8
+1 -
A V
[1] [2] [3]
This parameter is guaranteed by design. For level shifting N-FET. This measurement is performed with a 0.1 F external capacitor on pin TMDS_BIAS.
Table 7. Enable circuit VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VIH VIL IIL ILI Ci
[1]
Parameter HIGH-level input voltage LOW-level input voltage LOW-level input current input leakage current input capacitance
Conditions HIGH = enable LOW = disable VI = 0.2 V; VCC(3V3) = 5.5 V VI = 3 V or 0 V
Min 0.7 x VCC(3V3) -0.5 -1 -
Typ 10 +0.1 3
Max VCC(5V0) + 0.5 0.3 x VCC(3V3) +1 7
Unit V V A A pF
Board side: input pin ENABLE[1]
The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed.
Table 8. Hot Plug control circuit VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol VIH VIL IIL ILI Ci Parameter HIGH-level input voltage LOW-level input voltage LOW-level input current input leakage current input capacitance VI = 3 V or 0 V Conditions HIGH = Hot Plug off LOW = Hot Plug on VI = 2.0 V; VCC(3V3) = 5.5 V Min 0.7 x VCC(3V3) -0.5 -1 Typ 10 +0.1 4 Max VCC(5V0) + 0.5 0.3 x VCC(3V3) +1 7 Unit V V A A pF Board side: input pin HOT_PLUG_DET_IN
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
9 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
Table 8. Hot Plug control circuit ...continued VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol ILI Ci Von Parameter input leakage current input capacitance on-state voltage VI = 3 V or 0 V II = 5 mA Conditions Min -1 Typ +0.1 6 400 Max +1 7 Unit A pF mV Connector side: output pin HOT_PLUG_DET_OUT
9. Dynamic characteristics
Table 9. DDC circuits VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Board side to connector side; see Figure 4 Pins DDC_CLK_IN to DDC_CLK_OUT and DDC_DAT_IN to DDC_DAT_OUT tPLH tPHL tTLH tTHL LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW to HIGH transition time HIGH to LOW transition time RL = 1.35 k; CL = 50 pF
[1] [1] [1]
150 125 90 2
270 210 110 3
300 225 130 5
ns ns ns ns
Pins DDC_CLK_OUT and DDC_DAT_OUT
Connector side to board side; see Figure 5 Pins DDC_CLK_OUT to DDC_CLK_IN and DDC_DAT_OUT to DDC_DAT_IN tPLH tPHL tTLH tTHL tsu th LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW to HIGH transition time HIGH to LOW transition time set-up time hold time pin ENABLE = HIGH before start condition pin ENABLE = HIGH after stop condition
[1] [1]
90 20 100 2 100 100
110 30 120 3 -
130 40 140 5 -
ns ns ns ns ns ns
Pins DDC_CLK_IN and DDC_DAT_IN
Enable: pin ENABLE
[2]
[2]
[1] [2]
Typical values were measured with VCC(3V3) = 3.3 V; VCC(5V0) = 5.0 V. Pin ENABLE should only change state when the DDC-bus is in an idle state.
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
10 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
9.1 AC Waveforms
3.3 V
input: board side 0.7 V 5.0 V
tPLH
output: connector side 1.5 V
001aag034
a. Propagation delay tPLH
input: board side
3.3 V
1.65 V
0.1 V output: connector side tPHL tPLH 5.0 V 80 %
(1)
2.5 V 0.3VCC(5V0) 20 % VOL tTHL tTLH
001aag035
(1) Dotted line indicates effect without slew rate accelerator.
b. Propagation delay tPHL and transition time Fig 4. Board side to connector side operation
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
11 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
output: connector side
5.0 V
0.3VCC(5V0) VOL 3.3 V 80 % 1.65 V 20 % VIL tTHL tTLH
001aag036
input: board side
tPHL
tPLH
Propagation delay output to input and transition time input
Fig 5.
Connector side to board side operation
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
12 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
10. Application information
10.1 TMDS
To protect the TMDS lines and also to comply with the impedance requirements of the HDMI specification, the IP4778CZ38 provides ESD protection with a low capacitive load. The dominant value for the TMDS line impedance is the capacitive load to ground. The IP4778CZ38 has a capacitive load of only 0.7 pF.
TMDS_D2+
TMDS_D1+
TMDS_BIAS
TMDS_D0+
TMDS_CLK+ VCC(5V0)
TMDS_D2-
TMDS_D1-
TMDS_GND
TMDS_D0-
TMDS_CLK-
001aag039
Fig 6.
ESD protection of TMDS lines
10.2 DDC circuit
The DDC-bus circuit contains full capacitive decoupling between the HDMI connector and the DDC-bus lines on the PCB. The capacitive decoupling ensures that the maximum capacitive load is within the 50 pF maximum of the HDMI specification. The slew rate accelerator supports high capacitive load on the HDMI cable side. Various HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a capacitive load of up to 6 nF. The slew rate accelerator boosts the DDC signal independent of which side of the bus is releasing the signal. The DDC module provides a level shifting and a multiplex option which is enabled by the ENABLE signal.
TMDS_BIAS
VCC(5V0)
TMDS_BIAS
VCC(5V0)
SLEW RATE ACCELERATOR ENABLE DDC_CLK_OUT DDC_CLK_IN DDC_DAT_OUT
SLEW RATE ACCELERATOR ENABLE DDC_DAT_IN
001aag040
001aag041
a. DDC clock Fig 7.
IP4778CZ38_2
b. DDC data
DDC circuit
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
13 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
5.0 V
(1) (1)
0.3VCC(5V0)
001aag042
(1) Dotted line indicates effect without slew rate accelerator.
Fig 8.
DDC output waveform
10.3 Hot Plug driver circuit
The IP4778CZ38 includes a Hot Plug driver circuit that simplifies the Hot Plug application. The circuit can be connected directly to GPIO pins. The Hot Plug control input is actively pulled LOW to ensure that at system standby or startup, the Hot Plug signal is HIGH even if a GPIO pin is in a 3-state condition. For correct CEC handling, it is essential that the Hot Plug signal is at HIGH-level in Standby mode. The HDMI source requires a Hot Plug signal so that it can read out the EDID information to initiate a proper startup CEC sequence.
TMDS_BIAS
VCC(5V0)
VCC(3V3)
HOT_PLUG_DET_OUT
10 A
HOT_PLUG_DET_IN
001aag043
Fig 9.
Hot Plug driver circuit
10.4 CEC
The CEC signal can generate distortions caused by signal ringing in a 1 kHz domain. The CEC slew rate limiter ensures that a signal does not ring independently of the CEC slave that is releasing the signal. A MOSFET transistor implements the backdrive protection which blocks signals during a power-down state. The slew rate of the CEC-bus is controlled by a slew rate that is defined independently of the load (ohmic and capacitive) at the CEC-bus.
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
14 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
TMDS_BIAS
VCC(3V3)
CEC_OUT
CEC_IN
SLEW RATE LIMITER
001aag044
Fig 10. CEC module
(1)
(1)
0.8 V
001aag045
(1) Dotted line indicates effect without slew rate limiter.
Fig 11. CEC output waveform
10.5 Multiplexing
Up to 4 HDMI interface ports can exist on an HDMI receiver. The DDC and Hot Plug signals are both needed to support various HDMI connectors, multiplexing and switching of the TMDS lines. The CEC-bus has to remain functional in order to detect activity such as a brake in support.
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
15 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
ENABLE
input 1 input 2 input 3
DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN
ENABLE
DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN
ENABLE
DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN
DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN
001aag046
Fig 12. Example of multiplexing both DDC and Hot Plug
The combination of a TMDS switch and the IP4778CZ38 is a cost-effective way to attain various HDMI ports by using a single input HDMI receiver device. The ENABLE signal activates the HDMI DDC and Hot Plug lines at the port that is selected by the system controller.
10.6 Backdrive protection
The HDMI contains various signals which can partly supply current into an HDMI device that is powered down. Typically, the DDC lines and the CEC signals can force 5 V into the switched off device. The IP4778CZ38 ensures that at power-down, the critical signals are blocked to prevent any damage to the HDMI sink and HDMI source.
supply off HDMI source backdrive current HDMI ASIC
5V HDMI sink
I2C-bus ASIC
001aag047
Fig 13. Backdrive protection
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
16 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
10.7 Application schematic
Figure 14 shows a typical application where the IP4778CZ38 provides a simplified interface to an HDMI port. This application requires only a few external components to adapt the HDMI port to the parameters of the HDMI receiver device or HDMI multiplexer.
u/c: >3V3 = enabled 0V = disabled
VCC(5V0)
VCC(3V3)
BAV40
100 k
1.5 k
1.5 k
27 k
47 k
47 k
ENABLE TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_CLK- CEC_IN DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN
1 2 4 5 7 8
HDMI CONNECTOR 37 35 34 32 31 TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_CLK- CEC DDC_CLK DDC_DAT HOTPLUG_DET +5 V
IP4778CZ38
10 11 12 13 14 29 28 26 25
23 16 22 17 21 18 19 20 3, 6, 9, 12, 15, 24, 27, 30, 33, 36 7, 8
1 k
EDID
1, 2, 3, 4 6 5
100 100
1 F
001aah830
Fig 14. Schematic of IP4778CZ38 application
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
17 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
10.8 Typical application
IP4778CZ38
VCC(5V0) ENABLE TMDS_D2+ TMDS_D2- TMDS_D1+ TMDS_D1- TMDS_D0+ TMDS_D0- TMDS_CLK+ TMDS_CLK- CEC_IN DDC_CLK_IN DDC_DAT_IN HOT_PLUG_DET_IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 VCC(3V3) stand by 1 TMDS_D2+ TMDS_GND TMDS_D2- TMDS_D1+ TMDS_GND TMDS_D1- TMDS_D0+ TMDS_GND TMDS_D0- TMDS_CLK+ TMDS_GND TMDS_CLK- CEC n.c. DDC_CLK DDC_DAT GND +5 V HOTPLUG_DET
19
HDMI connector
Rdata 1.5 k
Rclock 1.5 k
RCEC 100 k
RCEC 27 k
Rdata 47 k
Rclock 47 k
RDDC 100
RHP 1 k
+3.3 V
+5.0 V
8765 EDID 1234
001aag049
Fig 15. Application showing optimized PCB microstrip lines
This application ensures that the EDID (stored in the EEPROM) can be read out in Standby mode, even if long cables are used, to guarantee correct CEC wake-up handling. To wake up the system from Standby to normal operation, the HDMI source has to first read the EDID in order to hand over the port ID via the CEC protocol. This ensures that the HDMI starts up and switches to the correct HDMI port to display the HDMI source which initiated the CEC wake-up sequence. The CEC-bus is enabled by activating the VCC(3V3) standby supply. The RF routing optimized pin position variant allows optimum design layout of the RF routing micro strips to ensure that the impedance of the TMDS lines remain within the specification limits. Part of the microstrips comprise a solid ground plane which is located beneath the device.
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
18 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
11. Test information
VCC(3V3) VCC(5V0) VCC
RL
G
VI
Rterm
DUT
VO
CL
001aah468
See Table 10 for test data. Rterm = termination resistance should be equal to output impedance Zo of the pulse generator. RL = load resistance. CL = load capacitance.
Fig 16. Test circuit for DDC and CEC lines Table 10. Test DDC lines CEC line Test data RL 1.35 k 27 k CL 50 pF 50 pF VCC VCC(5V0) VCC(3V3)
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
19 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
12. Package outline
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm
SOT510-1
D
E
A X
c y HE vMA
Z
38
20
A2 pin 1 index A1
(A 3)
A
Lp L
1
e bp
19
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 9.8 9.6 E (2) 4.5 4.3 e 0.5 HE 6.4 L 1 Lp 0.7 0.5 v 0.2 w 0.08 y 0.08 Z (1) 0.49 0.21
8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT510-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 05-11-02
Fig 17. Package outline SOT510-1 (TSSOP38)
IP4778CZ38_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
20 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
IP4778CZ38_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
21 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
Table 11. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 12. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 18.
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
22 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 13. Acronym ASIC CEC DDC DVD DVI EDID ESD FET GPIO HDM HDMI MOSFET RoHS TMDS Abbreviations Description Application Specific Integrated Circuit Consumer Electronics Control Data Display Channel Digital Video Disk Digital Video Interface Extended Display Identification Data ElectroStatic Discharge Field-Effect Transistor General Purpose Input/Output High-Definition Multimedia High-Definition Multimedia Interface Metal Oxide Semiconductor Field Effect Transistor Restriction of the use of certain Hazardous Substances Transition Minimized Differential Signaling
15. Glossary
HDMI sink -- Device which receives HDMI signals e.g. a TV set. HDMI source -- Device which transmit HDMI signal e.g. a DVD player.
IP4778CZ38_2 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
23 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
16. Revision history
Table 14. Revision history Release date 20090212 Data sheet status Product data sheet Change notice Supersedes IP4778CZ38_1 Document ID IP4778CZ38_2 Modifications:
* * * * * * * * * * *
Figure 1: updated Table 3: updated value Ptot Table 5: updated values Table 6: updated value SRr Table 7: updated values Table 8: updated values Table 9: updated values Section 10.3: updated text Figure 9: updated Figure 14: updated Figure 15: updated Objective data sheet -
IP4778CZ38_1
20080410
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
24 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.
17.4 Licenses
Purchase of NXP ICs with HDMI technology Use of an NXP IC with HDMI technology in equipment that complies with the HDMI standard requires a license from HDMI Licensing LLC, 1060 E. Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail: admin@hdmi.org.
17.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
IP4778CZ38_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 12 February 2009
25 of 26
NXP Semiconductors
IP4778CZ38
HDMI ESD protection, DDC buffering and hot plug control
19. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 9.1 10 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 11 12 13 13.1 13.2 13.3 13.4 14 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information. . . . . . . . . . . . . . . . . . 13 TMDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hot Plug driver circuit . . . . . . . . . . . . . . . . . . . 14 CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Backdrive protection . . . . . . . . . . . . . . . . . . . . 16 Application schematic . . . . . . . . . . . . . . . . . . . 17 Typical application. . . . . . . . . . . . . . . . . . . . . . 18 Test information . . . . . . . . . . . . . . . . . . . . . . . . 19 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 February 2009 Document identifier: IP4778CZ38_2

▲Up To Search▲

Price & Availability of IP4778CZ38V

	To Download IP4778CZ38V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .